Dual direction ESD protection capability is important in many applications, for example, in the case of interfaces and level shifters. A common device that meets this requirement is the DIACs, which is commonly implemented in a CMOS process with deep n-well or in the case of high voltage processes, is implemented with n-epitaxial or NISO isolation.
Two such prior art DIACs are shown in FIGS. 1 and 2. FIG. 1 shows a symmetrical CMOS DIAC that comprises a first p-well (RW) 100 and a second p-well (RW) 102 isolated from each other by an n-well (NW) 106 and a deep n-well (DNW) 110. N-wells 104, 108 extend on the outer sides of the RW 100 and the RW 102. An n+ region 120 and a p+ region 122 are formed in the RW 102. Similarly, an n+ region 124 and a p+ region 126 are formed in the RW 100. Thus the contact regions, which take the form of shorted n+ and p+ regions 120, 122 and 124, 126 are isolated by a dual blocking junction. The n-wells 104, 106, 108 are formed in a p-substrate 140, and as shown in FIG. 1, a p-well 130 is formed in the p-substrate 140. The p-well 130 is contacted through p+ region 128, which is connected to the n+ region 124 and p+ region 126. A floating n+ region 132 is formed between the RW's 100, 102.
FIG. 2 shows an asymmetrical DIAC as known in the art, which includes a single p-well (RW) 200 with an n-well on either side (NW 202 and NW 204), which extend downward to an isolating deep n-well (DNW) 210. The NWs 202, 204 and DNW 210 are formed in a p-substrate 240, as is a p-well 230. An n+ region 220 and p+ region 222 are formed in the RW 200 and are connected to each other. A p+ region 228 and an n+ region 224 are in turn formed in the PW 230, and are also connected to each other. Thus the contact regions defined by the shorted n+ 220 and p+ 222 are again isolated from the shorted n+ region 224 and p+ region 228. A floating n+ region 250 is formed between the RW 200 and the PW 230.
During operation the PAD can be above or below ground and it is important to be able to protect the PAD during both positive and negative voltage swings. However, CMOS DIACs suffer from very high triggering voltages and often require second stage protection. Since the triggering voltage can be controlled by controlling the breakdown of the diffusion blocking junction, one prior art technique in reducing the breakdown and triggering voltage is to make use of a SiGe BJT. However, there is no general solution to reducing the triggering voltage below the n+ to p-well breakdown.